You're looking for information on the PCI Express M.2 specification, specifically Revision 5.0, Version 1.0. Here's what I found:
| Aspect | Detail | |--------|--------| | | 32 GT/s per lane; x4 = ~15.75 GB/s raw bandwidth | | Keying | Same M-key and B+M-key physical design, but tighter electrical tolerances | | Power | Up to 14W sustained; L1.2 substate < 5 mW | | Backward Compatible | Yes, to PCIe 4.0 and 3.0 (electrically and via link negotiation) | | Access | PCI-SIG members only; not a public PDF | pci express m.2 specification revision 5.0 version 1.0 pdf
Non-members can sometimes view via PCI-SIG disclosures or through corporate technical partners. Unauthorized public distribution of the PDF violates PCI-SIG IP policy. You're looking for information on the PCI Express M
You're looking for information on the PCI Express M.2 specification, specifically Revision 5.0, Version 1.0. Here's what I found:
| Aspect | Detail | |--------|--------| | | 32 GT/s per lane; x4 = ~15.75 GB/s raw bandwidth | | Keying | Same M-key and B+M-key physical design, but tighter electrical tolerances | | Power | Up to 14W sustained; L1.2 substate < 5 mW | | Backward Compatible | Yes, to PCIe 4.0 and 3.0 (electrically and via link negotiation) | | Access | PCI-SIG members only; not a public PDF |
Non-members can sometimes view via PCI-SIG disclosures or through corporate technical partners. Unauthorized public distribution of the PDF violates PCI-SIG IP policy.